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16k x 8/9 dual-port static ram with sem, int, busy CY7C006 cy7c016 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 december 22, 1999 features ? true dual-ported memory cells which allow simultaneous reads of the same memory location 16k x 8 organization (CY7C006) 16k x 9 organization (cy7c016) 0.65-micron cmos for optimum speed/power high-speed access: 15 ns low operating power: i cc = 140 ma (typ.) fully asynchronous operation automatic power-down ttl compatible expandable data bus to 16/18 bits or more using master/slave chip select when using more than one device busy arbitration scheme provided semaphores included to permit software handshaking between ports int flag for port-to-port communication available in 68-pin plcc (7c006), 64-pin (7c006) and 80-pin (7c016) tqfp pin compatible and functional equivalent to idt7006/idt7016 functional description the CY7C006 and cy7c016 are high-speed cmos 16k x 8 and 16k x 9 dual-port static rams. various arbitration schemes are included on the CY7C006/016 to handle situa- tions when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchro- nous access for reads and writes to any location in memory. the CY7C006/016 can be utilized as a standalone 128-/144-kbit dual-port static ram or multiple devices can be combined in order to function as a 16-/18-bit or wider mas- ter/slave dual-port static ram. an m/s pin is provided for im- plementing 16-/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multi- processor designs, communications status buffering, and du- al-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags, busy and int , are provided on each port. busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) per- mits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared re- source is in use. an automatic power-down feature is con- trolled independently on each port by a chip enable (ce ) pin or sem pin. the CY7C006 and cy7c016 are available in 68-pin plcc (CY7C006), 64-pin (CY7C006) tqfp, and 80-pin (cy7c016) tqfp. notes: 1. busy is an output in master mode and an input in slave mode. 2. interrupt: push-pull output and requires no pull-up resistor. c006-1 r/w l ce l oe l a 13l a 0l a 0r a 13r r/w r ce r oe r ce r oe r ce l oe l r/w l r/w r i/o 7l i/o 0l i/o 7r i/o 0r interrupt semaphore arbitration control i/o control i/o memory array address decoder address decoder sem l sem r busy l busy r int l int r m/s (7c016) i/o 8l i/o 8r (7c016) [1,2] [1,2] [2] [2] logic block diagram with sem, in t, b usy
CY7C006 cy7c016 2 pin configurations note: 3. i/o for cy7c016 only. 64-pin tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 16 gnd oe r i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r i/o 6r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r i/o 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r a 13r ce r sem r r/w r v cc oe l i/o 1l i/o 0l a 5l a 12l a 11l a 10l a 9l a 8l a 7l a 6l a 13l ce l sem l r/w l CY7C006 c006-2 top view 68-pin plcc v cc oe l i/o 1l i/o 0l a 12l a 11l a 10l a 9l a 8l a 7l a 6l a 13l ce l sem l r/w l i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r gnd oe r i/o 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r a 13r ce r sem r r/w r a 5l nc nc(i/o 8l ) nc i/o6 r CY7C006 24 25 26 10 11 12 13 14 15 48 47 46 45 44 40 41 27 42 28 43 29 30 31 32 33 68 34 67 35 66 36 65 37 64 38 63 39 62 61 16 59 58 57 56 55 54 53 52 51 50 49 60 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 nc(i/o 8r ) c006-3 [3] [3]
CY7C006 cy7c016 3 pin definitions pin configurations (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 36 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 44 45 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 64 65 63 62 61 80-pin tqfp top view i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r 2r i/o 3r i/o 4r 5r gnd v cc v cc oe l i/o 0l i/o 8l a 5l a 12l a 11l a 10l a 9l a 8l a 7l a 6l ce l sem l r/w l a 4l a 3l a 2l a 1l a 0l gnd busy l m/s a 0r a 1r a 2r a 3r a 4r int l gnd oe r i/o 6r a 12r a 11r a 10r a 9r a 8r a 7r a 6r nc ce r sem r r/w r cy7c016 busy r int r i/o 8r nc a nc nc nc nc nc nc nc nc nc c006-4 nc a 5r i/o 7r nc i/o i/o nc i/o 1l 13r a 13l left port right port description i/o 0l ? 7l(8l) i/o 0r ? 7r(8r) data bus input/output a 0l ? 13l a 0r ? 13r address lines ce l ce r chip enable oe l oe r output enable r/w l r/w r read/write enable sem l sem r semaphore enable. when asserted low, allows access to eight sema- phores. the three least significant bits of the address lines will determine which semaphore to write or read. the i/o 0 pin is used when writing to a semaphore. semaphores are requested by writing a 0 into the respective location. int l int r interrupt flag. int l is set when right port writes location 3ffe and is cleared when left port reads location 3ffe. int r is set when left port writes location 3fff and is cleared when right port reads location 3fff. busy l busy r busy flag m/s master or slave select v cc power gnd ground
CY7C006 cy7c016 4 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... ? 0.5v to +7.0v dc input voltage [4] ......................................... ? 0.5v to +7.0v output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma notes: 4. pulse width < 20 ns. 5. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . selection guide 7c006-15 7c016-15 7c006-25 7c016-25 7c006-35 7c016-35 7c006-55 7c016-55 maximum access time (ns) 15 25 35 55 maximum operating current (ma) 260 220 210 200 maximum standby current for i sb1 (ma) 70 60 50 40 operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial ? 40 c to +85 c 5v 10% electrical characteristics over the operating range 7c006-15 7c016-15 7c006-25 7c016-25 parameter description test conditions min. typ. max. min. typ. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 0.4 v v ih 2.2 2.2 v v il input low voltage 0.8 0.8 v i ix input leakage current gnd v i v cc ? 10 +10 ? 10 +10 a i oz output leakage current outputs disabled, gnd v o v cc ? 10 +10 ? 10 +10 a i cc operating current v cc = max., i out = 0 ma outputs disabled com ? l 170 260 160 220 ma ind 160 270 i sb1 standby current (both ports ttl levels) ce l and ce r v ih , f = f max [5] com ? l 50 70 40 60 ma ind 40 75 i sb2 standby current (one port ttl level) ce l or ce r v ih , f = f max [5] com ? l 110 170 90 130 ma ind 90 150 i sb3 standby current (both ports cmos levels) both ports ce and ce r v cc ? 0.2v, v in v cc ? 0.2v or v in 0.2v, f = 0 [5] com ? l 3 15 3 15 ma ind 3 15 i sb4 standby current (one port cmos level) one port ce l or ce r v cc ? 0.2v, v in v cc ? 0.2v or v in 0.2v, active port outputs, f = f max [5] com ? l 100 150 80 120 ma ind 80 130
CY7C006 cy7c016 5 electrical characteristics (continued) 7c006-35 7c016-35 7c006-55 7c016-55 parameter description test conditions min. typ. max. min. typ. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 0.4 v v ih 2.2 2.2 v v il input low voltage 0.8 0.8 v i ix input leakage current gnd v i v cc ? 10 +10 ? 10 +10 a i oz output leakage current outputs disabled, gnd v o v cc ? 10 +10 ? 10 +10 a i cc operating current v cc = max., i out = 0 ma outputs disabled com ? l 150 210 140 200 ma ind 150 250 140 240 i sb1 standby current (both ports ttl levels) ce l and ce r v ih , f = f max [5] com ? l 30 50 20 40 ma ind 30 65 20 55 i sb2 standby current (one port ttl level) ce l or ce r v ih , f = f max [5] com ? l 80 120 70 100 ma ind 80 130 70 115 i sb3 standby current (both ports cmos levels) both ports ce and ce r v cc ? 0.2v, v in v cc ? 0.2v or v in 0.2v, f = 0 [5] com ? l 3 15 3 15 ma ind 3 15 3 15 i sb4 standby current (one port cmos level) one port ce l or ce r v cc ? 0.2v, v in v cc ? 0.2v or v in 0.2v, active port outputs, f = f max [5] com ? l 70 100 60 90 ma ind 70 110 60 95 capacitance [6] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf ac test loads and waveforms note: 6. tested initially and after any design or process changes that may affect these parameters. 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) 5v output c= 30 pf v th =1.4v output c=30 pf (b) th venin equivalent (load) (c) three-state delay (load 3) c = 30 pf output load (load 2) c006-5 c006-6 c006-7 c006-8 c006-9 5v output c= 5pf r1=893 ? r2=347 ? r th =250 ? r1=893 ? r2=347 ?
CY7C006 cy7c016 6 switching characteristics over the operating range [7] 7c006-15 7c016-15 7c006-25 7c016-25 7c006-35 7c016-35 7c006-55 7c016-55 parameter description min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 15 25 35 55 ns t aa address to data valid 15 25 35 55 ns t oha output hold from address change 3 3 3 3 ns t ace ce low to data valid 15 25 35 55 ns t doe oe low to data valid 10 13 20 25 ns t lzoe [8, 9, 10] oe low to low z 3 3 3 3 ns t hzoe [8, 9, 10] oe high to high z 10 15 15 25 ns t lzce [8, 9, 10] ce low to low z 3 3 3 3 ns t hzce [8, 9, 10] ce high to high z 10 15 15 25 ns t pu [10] ce low to power-up 0 0 0 0 ns t pd [10] ce high to power-down 15 25 35 55 ns write cycle t wc write cycle time 15 25 35 55 ns t sce ce low to write end 12 20 30 45 ns t aw address set-up to write end 12 20 30 45 ns t ha address hold from write end 0 0 0 0 ns t sa address set-up to write start 0 0 0 0 ns t pwe write pulse width 12 20 25 40 ns t sd data set-up to write end 10 15 15 25 ns t hd [11] data hold from write end 0 0 0 0 ns t hzwe [9, 10] r/w low to high z 10 15 20 25 ns t lzwe [9, 10] r/w high to low z 3 3 3 3 ns t wdd [12] write pulse to data delay 30 50 60 80 ns t ddd [12] write data valid to read data valid 25 30 35 60 ns busy timing [13] t bla busy low from address match 15 20 20 30 ns t bha busy high from address mismatch 15 20 20 30 ns t blc busy low from ce low 15 20 20 30 ns t bhc busy high from ce high 15 17 25 30 ns t ps port set-up for priority 5 5 5 5 ns t wb r/w low after busy low 0 0 0 0 ns t wh r/w high after busy high 13 17 25 30 ns t bdd [14] busy high to data valid note 13 note 13 note 13 note 13 ns notes: 7. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i oi /i oh and 30-pf load capacitance. 8. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 9. test conditions used are load 3. 10. this parameter is guaranteed but not tested. 11. must be met by the device writing to the ram under all operating conditions. 12. for information on part-to-part delay through ram cells from writing port to reading port, refer to read timing with port-to -port delay waveform. 13. test conditions used are load 2. 14. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual).
CY7C006 cy7c016 7 interrupt timing [13] t ins int set time 15 25 25 30 ns t inr int reset time 15 25 25 30 ns semaphore timing t sop sem flag update pulse (oe or sem ) 10 10 15 20 ns t swrd sem flag write to read time 5 5 5 5 ns t sps sem flag contention window 5 5 5 5 ns switching characteristics over the operating range [7] (continued) 7c006-15 7c016-15 7c006-25 7c016-25 7c006-35 7c016-35 7c006-55 7c016-55 parameter description min. max. min. max. min. max. min. max. unit switching waveforms notes: 15. r/w is high for read cycle. 16. device is continuously selected ce = low and oe = low. this waveform cannot be used for semaphore reads. 17. address valid prior to or coincident with ce transition low. 18. ce l = l, sem = h when accessing ram. ce = h, sem = l when accessing semaphores. t rc t aa t oha data valid previous data valid data out address c006-10 read cycle no. 1 (either port address access) [15, 16] t ace t lzoe t doe t hzoe t hzce data valid data out sem or ce oe t lzce t pu i cc i sb t pd c006-11 read cycle no. 2 (either port ce /oe access) [15, 17, 18]
CY7C006 cy7c016 8 notes: 19. busy = high for the writing port. 20. ce l = ce r = low. 21. the internal write time of the memory is defined by the overlap of ce or sem low and r/w low. both signals must be low to initiate a write, and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write. 22. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during a r/w controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified t pwe . 23. r/w must be high during all address transitions. switching waveforms (continued) va lid t ddd t wdd match match r/w r data in r data outl c006-12 t wc address r t pwe va lid t sd t hd address l read timing with port-to-port delay (m/s =l) [19, 20] c006-13 t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha t hzoe t lzoe sem or ce r/w address oe data out data in write cycle no. 1: oe three-state data i/os (either port) [21, 22, 23]
CY7C006 cy7c016 9 notes: 24. data i/o pins enter high-impedance when oe is held low during write. 25. ce = high for the duration of the above timing (both write and read cycle). switching waveforms (continued) t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance sem or ce r/w address data out data in t lzwe data valid c006-14 write cycle no. 2: r/w three-state data i/os (either port) [20, 22, 24] t sop sem r/w oe i/o 0 c006-15 valid address valid address t hd data in va lid data out va lid t oha a 0 ? a 2 t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle semaphore read after write timing, either side [25] t aw t aa
CY7C006 cy7c016 10 notes: 26. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 27. semaphores are reset (available to both ports) at cycle start. 28. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side w ill control the sema phore. switching waveforms (continued) match c006-16 t sps a 0l ? a 2l match r/w l sem l a 0r ? a 2r r/w r sem r semaphore contention [26, 27, 28] va lid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe va lid t sd t hd address l t ps t bla t bha t bdd busy l c006-17 read with busy (m/s =high) [19] t pwe r/w busy t wb t wh write timing with busy input (m/s =low) c006-18
CY7C006 cy7c016 11 notes: 29. if t ps is violated, the busy signal w ill be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. 30. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 31. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce l ce r busy l ce r ce l address l,r c006-19 c006-20 ce l valid first: busy timing diagram no. 1 (ce arbitration) [29] address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: c006-21 c006-22 left addressvalid first: busy timing diagram no. 2 (address arbitration) [28]
CY7C006 cy7c016 12 switching waveforms (continued) interrupt timing diagrams write 3fff t wc right side clears int r : t ha read 3fff t rc t inr write 3fff t wc right side sets int l : left side sets int r : left side clears int l : read 3fff t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins c006-23 c006-24 c006-25 c006-26 [30] [30] [30] [ 31]
CY7C006 cy7c016 13 architecture the CY7C006/016 consists of a an array of 16k words of 8/9 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit indepen- dent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is pro- vided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the CY7C006/016 can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the CY7C006/016 has an auto- matic power-down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a valid write. a write operation is con- trolled by either the oe pin (see write cycle no.1 waveform) or the r/w pin (see write cycle no. 2 waveform). data can be written to the device t hzoe after the oe is deasserted or t hzwe after the falling edge of r/w . required inputs for non-contention operations are sum- marized in table 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; oth- erwise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe are asserted. if the user of the CY7C006/016 wishes to access a sema- phore flag, then the sem pin must be asserted instead of the ce pin. interrupts the interrupt flag (int ) permits communications between ports. when the left port writes to location 3fff(hex), the right port ? s inter- rupt flag (int r ) is set. this flag is cleared when the right port reads that same location. setting the left port ? s interrupt flag (int l ) is ac- complished when the right port writes to location 3ffe(hex). this flag is cleared when the left port reads location 3ffe(hex). the mes- sage at 3ffe(hex) and 3fff(hex) is user-defined. see ta bl e 2 for input requirements for int . int r and int l are push-pull outputs and do not require pull-up resistors to operate. busy the CY7C006/016 provides on-chip arbitration to resolve si- multaneous memory location access (contention). if both ports ? ce s are asserted and an address match occurs within t ps of each other the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not guaranteed which one. busy will be asserted t bla after an address match or t blc after ce is taken low. busy l and busy r in master mode are push-pull outputs and do not require pull-up re- sistors to operate. master/slave an m/s pin is provided in order to expand the word width by config- uring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external compo- nents. writing of slave devices must be delayed until after the busy input has settled (t bla ). otherwise, the slave chip may begin a write cycle during a contention situation. when presented a high input, the m/s pin allows the device to be used as a master and therefore the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the CY7C006/016 provides eight semaphore latches which are separate from the dual-port memory locations. sema- phores are used to reserve resources that are shared between the two ports.the state of the semaphore indicates that a re- source is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a 0 to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the sema- phore. the semaphore value will be available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a 0), it assumes control over the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore.when the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaphore, a 1 is written to cancel its request. table 1. non-contending read/write inputs outputs ce r/w oe sem i/o 0 ? 7/8 operation h x x h high z power-down h h l l data out read data in semaphore x x h x high z i/o lines disabled h x l data in write to semaphore l h l h data out read l l x h data in write l x x l illegal condition table 2. interrupt operation example (assumes busy l =busy r =high) left port right port function r/w ce oe a 0l ? 13l int r/w ce oe a 0r ? 13r int set left int x x x x l l l x 3ffe x reset left int x l l 3ffe h x l l x x set right int l l x 3fff x x x x x l reset right int x x x x x x l l 3fff h
CY7C006 cy7c016 14 semaphores are accessed by asserting sem low. the sem pin functions as a chip enable for the semaphore latches (ce must remain high during sem low). a 0 ? 2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access.when writing or reading a semaphore, the other ad- dress pins have no effect. when writing to the semaphore, only i/o 0 is used. if a 0 is written to the left port of an unused semaphore, a 1 will appear at the same semaphore address on the right port. that semaphore can now only be modified by the side showing 0 (the left port in this case). if the left port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both sides. however, if the right port had requested the semaphore (written a 0) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. ta bl e 3 shows sample semaphore operations. when reading a semaphore, all eight data lines output the semaphore value. the read value is latched in an output reg- ister to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. initialization of the semaphore is not automatic and must be reset during initialization program at power-up. all sema- phores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. table 3. semaphore operation example function i/o 0-7/8 left i/o 0-7/8 right status no action 1 1 semaphore free left port writes semaphore 0 1 left port obtains semaphore right port writes 0 to semaphore 0 1 right side is denied access left port writes 1 to semaphore 1 0 right port is granted access to semaphore left port writes 0 to semaphore 1 0 no change. left port is denied access right port writes 1 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore address right port writes 0 to semaphore 1 0 right port obtains semaphore right port writes 1 to semaphore 1 1 no port accessing semaphore left port writes 0 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore ordering information 16k x8 dual-port sram speed (ns) ordering code package name package type operating range 15 CY7C006-15ac a65 64-lead thin quad flat package commercial CY7C006-15jc j81 68-lead plastic leaded chip carrier 25 CY7C006-25ac a65 64-lead thin quad flat package commercial CY7C006-25jc j81 68-lead plastic leaded chip carrier CY7C006-25ai a65 64-lead thin quad flat package industrial CY7C006-25ji j81 68-lead plastic leaded chip carrier 35 CY7C006-35ac a65 64-lead thin quad flat package commercial CY7C006-35jc j81 68-lead plastic leaded chip carrier CY7C006-35ai a65 64-lead thin quad flat package industrial CY7C006-35ji j81 68-lead plastic leaded chip carrier 55 CY7C006-55ac a65 64-lead thin quad flat package commercial CY7C006-55jc j81 68-lead plastic leaded chip carrier CY7C006-55ai a65 64-lead thin quad flat package industrial CY7C006-55ji j81 68-lead plastic leaded chip carrier
CY7C006 cy7c016 15 document #: 38-00416-b ordering information (continued) 16k x9 dual-port sram speed (ns) ordering code package name package type operating range 15 cy7c016-15ac a80 80-lead thin quad flat package commercial 25 cy7c016-25ac a80 80-lead thin quad flat package commercial cy7c016-25ai a80 80-lead thin quad flat package industrial 35 cy7c016-35ac a80 80-lead thin quad flat package commercial cy7c016-35ai a80 80-lead thin quad flat package industrial 55 cy7c016-55ac a80 80-lead thin quad flat package commercial cy7c016-55ai a80 80-lead thin quad flat package industrial package diagrams 64-lead thin plastic quad flat pack (14 x 14 x 1.4 mm) a65 51-85046-b
CY7C006 cy7c016 ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 80-pin thin plastic quad flat pack a80 51-85065-b 68-lead plastic leaded chip carrier j81 51-85005-a

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